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（转）用SystemVerilog做验证项目实例

已有 10707 次阅读| 2012-3-27 23:07

http://socvista.com/bbs/viewthread.php?tid=3105

用Systemverilog做验证项目实例

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接触了一下systemverilog，还是第一次，把自己的整个接触过程记录一下。梳理清楚一些关键的要点。
我们的systemverilog验证是一个印度哥们给做的，有几年经验了。
作为使用的初体验，首先是运行仿真，很简单，就是make 一下而已。
比如：
gmake my_test
当然，懂点Linux知识的都知道，执行这个命令的当前目录下，必须有形如Makefile之类的文件。该文件里面记录了需要做的实际工作。
好吧，让我们来看看这个Makefile。

Makefile的前言说明

这个Makefile是synopsys提供的模板，看上去非常好用，你只要按部就班提供实际项目的参数就可以了。我们来看这个文件的头部说明：

#-----------------------------------------------------------------------------
#
# SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
# Synopsys, Inc., and is fully protected under copyright and trade secret
# laws. You may not view, use, disclose, copy, or distribute this file or
# any information contained herein except pursuant to a valid written
# license from Synopsys.
#
#-----------------------------------------------------------------------------
#
# Filename : $Id: Makefile,v 1.0 2006/07/18 23:59:59 vangundy Exp $
#
# Created by  : Synopsys Inc. 07/17/2006
#             $Author: vangundy $
#
# Description : Demonstrates Verilog DUT and SVTB using VCS
#
#  The Makefile works on two seperate flows.  The DEBUG flow is intended to be used
#  during debugging of a testcase and/or the DUT.  The REGRESSION flow is used
#  during regression runs and collects coverage data.
#
#  The DEBUG flow turns on VPD dumping and turns off coverage collection.  After
#  building a testcase using the debug targets, you can debug the TB and the DUT
#  source code using the testbench debugger and DVE.  Of course, you can turn on
#  coverage metrics and run in debug mode by changing compile and runtime options
#  in the makefile.  These changes are independent of the regression flow so that
#  the regressions will still run optimally without the interference of VPD
#  dumping.
#
#  The REGRESSION flow turns off VPD dumping and turns on Coverage Metrics and TB
#  coverage collection.  This flow is intended to support verification engineers who
#  are working through the regression process and are interested in coverage
#  collection and urg.
#
#  Command Line
#  ------------
#  The Makefile supports the following command line
#
#  % make target_name_* <SEED=xxx> <DEFINES=xxxx>
#
#  Where target_name is the name of a testcase located in the test directory.  Every
#  test in the test directory is named using test_{test_name}.  All of the test targets
#  are listed in the TEST TARGETS section of the makefile.
#
#  Compile and Run Testcases
#  -------------------------
#  To compile and run a tescase use the test_* and regress_test_* targets.
#
#  % make test_1          // Builds and runs test 1 with VPD dumping and debug on
#  % make regress_test_1 // Builds and runs test 1 with coverage turned on
#
#  Debugging Testcases
#  -------------------
#  You can use DVE and the testbench debugger to visualize waveforms and testbench
#  execution.  You must first build the testbench using the make compile_* command.
#
#  % make compile_1       // Builds test 1 for debugging
#
#  Once you have built the environment with the proper debug switches, you can use DVE
#  and the testbench debugger.
#
#  % make gui_1          // Debug test 1 with DVE
#  % make tb_gui_1       // Debug test 1 with the testbench debugger
#  % make both_guis_1    // Debug using both guis
#  % make pp_1          // Debug using the VPD file
#
#  If you want, you can turn on coverage for the DEBUG flow by uncommenting the
#  coverage flag in the makefile.  If you do this, you can still look at coverage.
#  This may be useful in helping those who are debugging coverage related issues.
#
#  % make urg             // Visualize coverage data from debug runs
#
#  Regression Testcases
#  --------------------
#  Regression tests are used to collect coverage information.  To build a testcase
#  for coverage collection use a command similar to the following.
#
#  % make regress_build_1  // Build and run a regression test with a default seed
#  Once the test has been built, you can run it again with a new seed.
#
#  % make regress_run_1 SEED=1234
#
#  After running one or more regression runs, you can visualize the coverage data
#  using urg and the following command
#
#  % make regress_urg
#-----------------------------------------------------------------------------

#-----------------------------------------------------------------------------
#
# HOW TO REUSE THIS FILE ON ANOTHER DUT
#
# STEP 1:  Update the file locations as required
# STEP 2:  Update the DUT section with directory and source location info
# STEP 3:  Update the TB section with directory and source location info
# STEP 4:  Update the Coverage section with name of dut top (eg top.dut)
# STEP 5:  Add test targets to the debug and regression targets section
# STEP 5:  Adjust the debug and regression compile and run time arguments
# STEP 7:  Adjust command line options as required
# STEP 8:  Update the env class so that it extends dkm_env
#    You will need to have a copy of the dkm directory and it should
#       be located at $(TB_SRC_DIR)/dkm
#       a) Add [`include "dkm_env.sv"]
#       b) Add [extends dkm_env] to the environment class definition
#          c) Call the super.new("name") from the constructor
# STEP 9:  Run the debug and regression targets
#          % make testbench_target_*
#
#-----------------------------------------------------------------------------

Step by Step 来创建自己的Makefile

看了上文，大家应该可以简单了解这个Makefile的功能了。接下来就按照step1~9来填空即可。

.PHONY : default help clean regress_clean
default: help

#-----------------------------------------------------------------------------
#
# DIRECTORIES
#
#-----------------------------------------------------------------------------
OUTPUT_DIR    = ./output
COV_DIR       = ./coverage
LOG_DIR       = ./logs

# Set this to the location where you installed the designware models.  This
# depends on whether you ran the setup_vip_dw_home to install the models or
# the setup_vip_here script.
#DW_MODELS_DIR = $(DESIGNWARE_HOME)
DW_MODELS_DIR = /user/synopsys/designware
#DESIGNWARE_HOME = ~synopsys/bk/designware
#DW_MODELS_DIR = ./designware

#----------------------------------------------------------------------------
# DEVICE UNDER TEST
#-----------------------------------------------------------------------------
DUT_SRC_DIR    = ./source/verilog

DUT_SRC       = -f $(DUT_SRC_DIR)/rtl_list.f
DUT_INC          += +incdir+/user/myproj/PROJECT/RTL/SRC/mymodule/
DUT_INC          += +incdir+/user/myproj/PROJECT/RTL/SRC/mymodule/mymodule_inc.v

DUT_CMP_OPTIONS += +libext+.v
#DUT_CMP_OPTIONS  += -timescale=1ps/1ps
#DUT_CMP_OPTIONS  += -override_timescale=1ps/1ps

#-----------------------------------------------------------------------------
# TESTBENCH
#-----------------------------------------------------------------------------
TB_SRC_DIR    = ./source/svtb

# AXI TESTBENCH, VIP Sources first
#TB_SRC       += -f $(TB_SRC_DIR)/mac_if_tb/vip/gslv_model_package.f
TB_SRC       += $(TB_SRC_DIR)/mpdu_trx_tb/tests/mpdu_tb_top.sv
TB_SRC       += $(TB_SRC_DIR)/mpdu_trx_tb/tests/$(TB_TEST).sv

TB_INC       += +incdir+$(TB_SRC_DIR)/mpdu_trx_tb/vip
TB_INC       += +incdir+$(TB_SRC_DIR)/mpdu_trx_tb/env
TB_INC       += +incdir+$(TB_SRC_DIR)/mpdu_trx_tb/tests

TB_INC          += +incdir+$(DW_MODELS_DIR)/include/svtb
TB_INC          += +incdir+$(DW_MODELS_DIR)/include/verilog
TB_INC          += +incdir+$(DW_MODELS_DIR)/svtb

#TB_CMP_OPTIONS += -tb_timescale=1ns/1ps
#TB_CMP_OPTIONS += -lca Y-2006.06-SP2
TB_CMP_OPTIONS += +pkgdir+$(DW_MODELS_DIR)/include/svtb
TB_CMP_OPTIONS += -ntb_incdir $(DW_MODELS_DIR)/include/vera

TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/vmt/latest/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_master_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_master_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_slave_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_slave_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_monitor_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_monitor_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_port_monitor_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_port_monitor_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_interconnect_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir $(DESIGNWARE_HOME)/vip/amba/latest/axi_interconnect_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_master_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_slave_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_monitor_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_bus_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_master_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_slave_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_monitor_rvm_vera_vmt/vera/src
TB_CMP_OPTIONS += -ntb_incdir ${DESIGNWARE_HOME}/vip/amba/latest/ahb_bus_rvm_vera_vmt/vera/src

TB_CMP_OPTIONS += -ntb_define NTB
TB_CMP_OPTIONS += -ntb_define DW_VIP_AXI_MAX_NO_MSTRS=6
TB_CMP_OPTIONS += -ntb_define DW_VIP_AXI_MAX_NO_SLVS=2
TB_CMP_OPTIONS += +define+DW_VIP_AXI_MAX_NO_MSTRS_6
TB_CMP_OPTIONS += +define+DW_VIP_AXI_MAX_NO_SLVS_2
TB_CMP_OPTIONS += -ntb_opts rvm
TB_CMP_OPTIONS += -ntb_opts dtm
TB_CMP_OPTIONS += -ntb_opts use_sigprop
TB_CMP_OPTIONS += -ntb_opts interop
TB_CMP_OPTIONS += -ntb_opts dw_vip
TB_CMP_OPTIONS += +define+NT

#
# AIP Related files and compilation options
#
#TB_CMP_OPTIONS += +incdir+../BP062-BU-01000-r0p0-00rel0/sva \
               +incdir+../BP062-BU-01000-r0p0-00rel0/verilog \
               ../BP062-BU-01000-r0p0-00rel0/sva/AxiPC.sv \
               ../BP062-BU-01000-r0p0-00rel0/verilog/Axi.v \
               ./source/svtb/platform_tb/env/Snps_armAXI_CheckerBind.sv

#${VCS_HOME}/packages/aip/DDR2_AIP/src/Snps_DDR2_Checker.sv \
               -assert enable_diag \
               +incdir+.+${VCS_HOME}/packages/aip/DDR2_AIP/src/ \
               ./source/svtb/platform_tb/env/Snps_DDR2_Bind.sv \
   +incdir+../BP062-BU-01000-r0p0-00rel0/sva \
               +incdir+../BP062-BU-01000-r0p0-00rel0/verilog \
               ../BP062-BU-01000-r0p0-00rel0/sva/AxiPC.sv \
               ../BP062-BU-01000-r0p0-00rel0/verilog/Axi.v \
               ./source/svtb/platform_tb/env/Snps_ARMAXI_CheckerBind.sv

#-----------------------------------------------------------------------------
# COVERAGE
#-----------------------------------------------------------------------------
COV_TREE       += '+tree mpdu_tb_top'
COV_CM_OPTIONS  += -cm line+cond+fsm+assert

#-----------------------------------------------------------------------------
# TEST TARGETS
#-----------------------------------------------------------------------------
# debug targets
test_1: compile_1 run_1
test_11: compile_11 run_11
test_12: compile_12 run_12
test_13: compile_13 run_13
test_14: compile_14 run_14
test_2: compile_2 run_2
test_perf: compile_perf run_perf

# regression targets
regress_test_1: regress_build_1 regress_run_1
regress_test_11: regress_build_11 regress_run_11
regress_test_12: regress_build_12 regress_run_12
regress_test_13: regress_build_13 regress_run_13
regress_test_14: regress_build_14 regress_run_14
regress_test_2: regress_build_2 regress_run_2
regress_test_perf: regress_build_perf regress_run_perf

#-----------------------------------------------------------------------------
#
# COMPILE AND RUN TIME ARGUMENTS
#
#-----------------------------------------------------------------------------
#--------------
# Debug
#--------------
# Debug compile time arguments
DBG_CMP          += $(COV_CMP_OPTIONS)
DBG_CMP          += -debug_all
//DBG_CMP          += -debug_pp
DBG_CMP          += +define+VPD_ON
#DBG_CMP          += +define+VPD_OFF
#DBG_CMP          += +define+LOG_FMT_OFF

# Debug run time arguments
DBG_RUN          += $(COV_SIM_OPTIONS)

#--------------
# Regression
#--------------
# Regression compile time arguments
REG_CMP          += $(COV_CMP_OPTIONS)
REG_CMP          += +define+VPD_OFF

# Regression run time arguments
REG_RUN          += $(COV_SIM_OPTIONS)

# Define where the coverage data is for URG
COV_DBG_DATA    += -dir $(COV_DIR)/debug/simv.vdb -dir  $(COV_DIR)/debug/simv.cm
COV_REG_DATA    += -dir $(COV_DIR)/regress/simv.vdb -dir  $(COV_DIR)/debug/simv.cm

#-----------------------------------------------------------------------------
#
# COMMAND LINE ARGUMENTS
#
#-----------------------------------------------------------------------------
SEED       = 766
#234567
#DEFINES    = "+rvm_log_default=DEBUG"
DEFINES    = "+vmm_log_default=DEBUG"
#DEFINES    = "+vmm_log_default=NOTE"
#DEFINES    = "+rvm_log_default=WARNING"
#DEFINES    = "+vmm_log_default=ERROR"

##############################################################################
##############################################################################
##############################################################################
##############################################################################
#
# PRIVATE
#
# You should not need to modify anything below this point
#
# The following code supports a SV DUT and SVTB.
#
##############################################################################
##############################################################################
##############################################################################
##############################################################################
DIR          = $(/user/synopsys/Gaon/Platform)

##########################################################################
#
# DEVICE UNDER TEST
#
##########################################################################

DUT_CMP_OPTIONS  += -sverilog +v2k
DUT_CMP_OPTIONS  += -o $(DUT_SIM_EXEC)
DUT_CMP_OPTIONS  += -Mdir=$(OUTPUT_DIR)/$(TB_TEST_ID)_csrc
DUT_CMP_OPTIONS  += -l $(LOG_DIR)/$(TB_TEST).cmp_log
DUT_CMP_OPTIONS  += +vcs+lic+wait +plusarg_save
DUT_CMP_OPTIONS  += $(DUT_INC)

DUT_SIM_OPTIONS  += -l $(LOG_DIR)/$(TB_TEST_ID).run_log
DUT_SIM_OPTIONS  += +vcs+lic+wait
DUT_SIM_OPTIONS  += +vpdfile+$(OUTPUT_DIR)/$(TB_TEST_ID).vpd

#DUT_SIM_OPTIONS  += +ntb_random_seed=$(SEED)

DUT_SIM_OPTIONS  += +ntb_random_seed_automatic
DUT_SIM_OPTIONS  += -assert nopostproc+report=$(LOG_DIR)/$(TB_TEST_ID).sva_log
DUT_SIM_OPTIONS  += -cm_assert_name $(TB_TEST_ID)
DUT_SIM_OPTIONS  += $(DEFINES)

DUT_SIM_EXEC    += $(OUTPUT_DIR)/$(TB_TEST)_simv

##########################################################################
#
# TESTBENCH
#
##########################################################################
TB_TEST       += test_$*
TB_TEST_ID    += $(TB_TEST)_$(SEED)

# VK ENVIRONMENT
TB_INC          += +incdir+$(TB_SRC_DIR)/vk

TB_CMP_OPTIONS +=  $(TB_INC)

##########################################################################
#
# COVERAGE
#
##########################################################################
#COV_CM_OPTIONS += +tb_cov_db_name=$(TB_TEST_ID)
COV_CM_OPTIONS += -cm_name $(TB_TEST_ID)

COV_CMP_OPTIONS  += $(COV_CM_OPTIONS) -cm_hier $(COV_HIER)

COV_SIM_OPTIONS  += $(COV_CM_OPTIONS)
COV_SIM_OPTIONS  += -cm_log $(LOG_DIR)/$(TB_TEST_ID).cm_log

COV_HIER       += $(OUTPUT_DIR)/vcm.cfg

# Coverage options for build and run with debug
COV_CM_DBG    += -cm_dir $(COV_DIR)/debug/simv.cm
#COV_CM_DBG    += -ova_dir $(COV_DIR)/debug/simv.vdb
#COV_CM_DBG    += +tb_cov_db_dir=$(COV_DIR)/debug/simv.vdb

# Coverage options for build and run with regressions
COV_CM_REG    += -cm_dir $(COV_DIR)/regress/simv.cm
COV_CM_REG    += -ova_dir $(COV_DIR)/regress/simv.vdb
COV_CM_REG    += +tb_cov_db_dir=$(COV_DIR)/regress/simv.vdb

##########################################################################
#
# DEBUG TARGETS
#
##########################################################################

compile_%:
echo $(COV_TREE) > $(COV_HIER);
vcs $(TB_CMP_OPTIONS) \
         $(DUT_CMP_OPTIONS) \
      $(DUT_SRC) \
      $(TB_SRC) \
      $(SVA_SRC) \
      $(SVA_OPTIONS) \
      $(COV_CM_DBG) \
      $(DBG_CMP)

run_%:
$(DUT_SIM_EXEC) $(DUT_SIM_OPTIONS) $(DBG_RUN) $(COV_CM_DBG)

gui_%:
$(DUT_SIM_EXEC) $(DUT_SIM_OPTIONS) $(DBG_RUN) $(COV_CM_DBG) \
-gui

tb_gui_%:
$(DUT_SIM_EXEC) $(DUT_SIM_OPTIONS) $(DBG_RUN) $(COV_CM_DBG) \
-tb_gui +ntb_debug_on_start

both_guis_%:
$(DUT_SIM_EXEC) $(DUT_SIM_OPTIONS) $(DBG_RUN) $(COV_CM_DBG) \
-gui \
-tb_gui +ntb_debug_on_start

new_gui_%:
$(DUT_SIM_EXEC) $(DUT_SIM_OPTIONS) $(DBG_RUN) $(COV_CM_DBG) \
-gui \
-tbug

pp_%:
dve -vpd $(OUTPUT_DIR)/$(TB_TEST_ID).vpd

urg:
urg $(COV_DBG_DATA)  -report $(COV_DIR)/debug/urgReport -lca
mozilla $(DIR)/$(COV_DIR)/debug/urgReport/dashboard.html &

dve_cov:
@echo ""
@echo "WARNING: Did you run this command?"
@echo ""
@echo " % source ./utils/setup_dve_cov"
@echo ""
dve -cov &

##########################################################################
#
# REGRESSION TARGETS
#
##########################################################################

regress_clean: clean
@rm -rf $(COV_DIR)/*
@mkdir -p $(COV_DIR)/debug
@mkdir -p $(COV_DIR)/regress
@mkdir -p $(LOG_DIR)
@mkdir -p $(OUTPUT_DIR)

regress_build_%:
echo $(COV_TREE) > $(COV_HIER);
vcs $(TB_CMP_OPTIONS) $(DUT_CMP_OPTIONS) \
      $(DUT_SRC) \
      $(TB_SRC) \
      $(SVA_SRC) \
      $(SVA_OPTIONS) \
      $(COV_CM_REG) \
      $(REG_CMP)

regress_run_%:
$(DUT_SIM_EXEC) $(DUT_SIM_OPTIONS) $(REG_RUN) $(COV_CM_REG)

regress_urg:
urg $(COV_REG_DATA) -grade -report $(COV_DIR)/regress/urgReport
mozilla $(DIR)/$(COV_DIR)/regress/urgReport/dashboard.html &

regress_dve_cov:
@echo ""
@echo "WARNING: Did you run this command?"
@echo ""
@echo " % source ./utils/setup_dve_cov"
@echo ""
dve -cov &

##########################################################################
#
# ADMINISTRATIVE
#
##########################################################################

help:
@echo =======================================================================
@echo  "       "
@echo  " USAGE: %make target_name_* <SEED=xxx> <DEFINES=xxxx>             "
@echo  "       "
@echo  " ------------------------ DEBUG TARGETS ----------------------------"
@echo  " test_*       => Compile TB and DUT files, runs the simulation.  "
@echo  " clean          => Clean the intermediate files.                "
@echo  " compile_*    => Compile the TB and DUT.                      "
@echo  " run_*          => Run the simulation.                            "
@echo  " gui_*          => Run simulation interactively with DVE.       "
@echo  " tb_gui_*       => Runs simulation interactively with TB Debugger. "
@echo  " both_guis_*    => Run both debuggers.                            "
@echo  " new_gui_*    => Run new integrated debuggers.                "
@echo  " pp_*          => Post process VPD with DVE.                   "
@echo  " urg          => Make a coverage report for debug runs.       "
@echo  " dve_cov       => Brings up DVE for coverage reporting.          "
@echo  "                                                                   "
@echo  " ----------------------- REGRESSION TARGETS ------------------------"
@echo  " regress_test_*  => Compile and run with coverage.                "
@echo  " regress_clean => Remove all coverage files.                   "
@echo  " regress_build_* => Build test_*.                                  "
@echo  " regress_run_* => Run test * collecting coverage information.    "
@echo  " regress_urg    => Make a coverage report for regression runs.    "
@echo  " regress_dve_cov => Brings up DVE for coverage reporting.          "
@echo  "                                                                   "
@echo  " -------------------- ADMINISTRATIVE TARGETS -----------------------"
@echo  " help          => Displays this message.                         "
@echo  " init          => Clean all files, including coverage files.    "
@echo  " tar          => Tar and zip kit and place at ../                "
@echo  "       "
@echo  " e.g.  gmake test_1                                              "
@echo =======================================================================

tar: clean
cd ..; \
tar cvf ${DIR}.tar ${DIR}; \