日志
zz Uncertainty在后端各个流程中的概况
| |
setting of uncertainty
○：预测值
●：已定值(已经确定的值不能考虑为Uncertainty)
+ ：规定值
- ：不需要的值
Note：
The PLL jitter needs not be cnsidered at hold check value,because the
same edge as the CK is checked.However,the pll jitter needs to be considered
when the edge is different than the CK or when the clock domain is different
than the CK.
The vaule is different among the PR flow.
| Uncertainty | ||||||||
| Clock | OCV | Xtalk | PLL | Gap between the | ||||
| skew | delay | Jitter | Pre And Actual | |||||
| Logic Synthesis | ○ | ○ | ○ | + | ○ | |||
| (Pre layout STA) | ||||||||
| Prototyping | ○ | ○ | ○ | + | - | |||
| P&R(Ideal) | ||||||||
| P&R(PropagatatedCLK) | ● | ○ | ○ | + | - | |||
| Setup without Xtalk SDF | ||||||||
| Hold without Xtalk SDF | ● | ○ | ○ | - | - | |||
| Sign Off | ● | ● | ● | + | - | |||
| Setup with Xtalk | ||||||||
| Hold with Xtalk | ● | ● | ● | + | - | |||
○：预测值
●：已定值(已经确定的值不能考虑为Uncertainty)
+ ：规定值
- ：不需要的值
Note：
The PLL jitter needs not be cnsidered at hold check value,because the
same edge as the CK is checked.However,the pll jitter needs to be considered
when the edge is different than the CK or when the clock domain is different
than the CK.
The vaule is different among the PR flow.
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