日志
8B10B encoder and decoder
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Specification
1. 8B/10B encoding and decoding.
2. 16B/20B and 32B/40B Cascaded encoding and decoding.
3. Running disparity can be forced.
4. Running disparity error output.
5. Code error output.
Status
1. RTL verilog source code completed
2. Verification completed
3. FPGA synthesis, place and route completed
4. Document completed
Contact
Email:hpiclab@sina.com
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