Specification

1.       Parameterized FIFO with the below options:

a)       Data width and address width.

b)       Synchronous or Asynchronous based on gray code.

c)       Normal or First word fall through.

d)       Area or Read timing optimization.

e)       Overflow and underflow protection.

f)        Programmable threshold for programmable full, almost full, programmable empty, almost empty.

g)       Reset value of write/read pointer.

2.       Status signals:

a)       Full, almost_full, prog_full, overflow.

b)       Empty, almost_empty, prog_empty, underflow.

3.       fifo remain data counter (only for Synchronous FIFO).

4.       Write/read pointer outputted and controllable externally.

Status

1.      RTL verilog source code completed

2.      Verification completed

3.    FPGA synthesis, place and route completed

4.    Document completed

Contact

Email: hpiclab@sina.com